Fashion model • san jose ca
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The average salary range is between $ 37,700 and $ 122,640 year , with the average salary hovering around $ 52,000 year .
Job Description
In Q4 2023, Intel announced PSG will be reported as a separate business unit beginning on January 1, 2024 with ongoing support from Intel. This position is associated to that standalone business strategy and is expected to fully transition to a standalone company at some time in the future.
Come join Altera working on Transaction Level Modeling for next generation FPGA and Structured ASIC technologies using Simics and SystemC. The Configuration and Embedded Solutions team is seeking an experienced modeler to help define and implement our pre-Silicon and customer deliverables for future solutions supported by our FPGA and Structured ASICs. This forward-looking and highly dynamic role provides unique opportunities to influence future product direction across several technologies and organizations while fundamentally driving advanced shift-left activities.
The role requires a self-starter with strong interpersonal communication, collaboration, and pathfinding skills along with a broad understanding of digital design and modeling. Experience in Intel FPGAs and Structured ASICs would be a distinct advantage.
In this role, you will have the opportunity to work directly with Silicon design teams, CAD tool teams, applications engineering and planning to define and influence new FPGA product development to drive holistic customer solutions that meet market requirements and delight customers.
Qualifications
Relevant experience can be obtained through schoolwork, classes, project work, internships or military experiences. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education Requirement:
Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or related field.
Minimum Qualifications:
7+ years of experience in digital design, digital verification, and at least 5 years in transaction level modeling such as languages such as SystemC, DML, or System Verilog.
Preferred Qualifications:
8+ years of experience in transaction level modeling using languages such as SystemC, DML, or SystemVerilog.
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