Validation manager • santa clara ca
TOP clients from our portfolio.We are currently looking for a.DFT & Post-Silicon Validation.Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? W... Show more
The ideal candidate should have hands-on experience in lab environments, debugging hardware issues, and validating silicon platforms.Perform board bring-up, hardware debugging, and validation activ... Show more
The System Integration and Architecture Team is seeking an experienced, bright, self-motivated, Sr.Manager of System Test and Validation to lead the System Test team.The successful candidate will o... Show more
Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics.Lab126 began in 2004 as a subsidiary of Amazon.Since then, we have produc... Show more
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Validation Manager (Platforms).Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver.Since its start as the Google Self-Driving Car Project in 200... Show more
At AMD, we believe technology has the power to solve the world's most important challenges.From advancing healthcare and scientific discovery to powering AI and the technologies people rely on ever... Show more
Senior Manager, Validation Engineering.Join a premier chip and silicon IP provider's Memory Interface Chip business unit.Work with leading inventors and engineers to develop products that enhance d... Show more
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The average salary range is between $ 119,136 and $ 176,426 year , with the average salary hovering around $ 140,516 year .
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently looking for a
DFT & Post-Silicon Validation to join one of our clients' team
Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.
Key Responsibilities
Leadership & Team Management
Lead and mentor the DFT and Post-Silicon engineering teams to drive innovation and efficiency.
Provide technical direction, ensuring alignment with organizational goals.
Foster a culture of continuous improvement and collaboration.
DFT Strategy & Execution
Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.
Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.
Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
Test Development & Implementation
Develop and implement test plans and test strategies at silicon, package, and system levels.
Define and develop automated test solutions for production and characterization.
Ensure test coverage for all product development stages, from pre-silicon to mass production.
Guarantee high yield on the final solution while considering chiplet complexities.
Cross-Functional Collaboration
Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
Collaborate with product management to ensure alignment with customer requirements and timelines.
Process Improvement & Innovation
Continuously explore and implement new DFT methodologies and manufacturing processes.
Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.
Reporting Structure
Reports to: Physical Implementation Team Manager
Receives reports from: DFT and Post-Silicon team members
Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.
Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.
Strong background in post-silicon test optimization and yield analysis.
Experience in defining and implementing test strategies for high-volume production.
Proficiency in RTL and testbench development using SystemVerilog and Verilog.
Strong scripting skills (Shell, Tcl, Python3).
Hands-on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus.
