RTL Design Lead for Data Center Chassis

Job Description

MediaTek's Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

The Data Center Chassis Lead will be responsible for architecting, adopting and designing chip / chiplet chassis building blocks for data center silicon. Key responsibilities include reviewing chassis building blocks, collaborating with chassis domain lead for architecting the version for data center, working with SoC / Chip / Chiplet design lead for integration requirement, execution plan and implementation, providing improvements based on analysis results, and conducting thorough quality design verification and documentation.

Requirement

• MS in Electrical Engineering / Computer Engineering or or related field.
• 5+ years of experience in designing transistor-level digital circuits.
• 3+ years of experience in hands on experience in architecting and designing chassis for data center silicon.
• Strong knowledge in SoC / Chip / Chiplet chassis : clock and reset, power and thermal management, out-of-band management, platform security, RAS, debug & test, eFuse control and distribution, and etc.
• Expert on designing with Verilog, SystemVerilog, Perl and Tcl script.
• Proficiency with EDA tools like VCS, Design compiler, and so on.
• Prior experience in all Front End activities and quality checks (eg : Lint, CDC...)
• Good understanding and working knowledge in other domains like DV and DFT, timing closure
• Able to provide timing constraints and work with PD teams to ensure RTL meets timing
• Strong debugging and scripting skills (Perl, Python, Tcl...)

Location : San Jose, California or Portland, Oregon

Equal Opportunity Statement : MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.