A leading technology company is seeking an ASIC Design Verification Engineer to optimize low latency SoCs for critical applications. The ideal candidate will have extensive experience in design verification, UVM, and a strong background in programming. In this role, you will contribute to groundbreaking technology that enhances real-time performance while working within a collaborative and innovative team environment.
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Senior ASIC Verification Engineer - Low-Latency SoC • San Francisco, California, United States