A company is looking for a Physical Verification Engineer (ASIC Design).
Key Responsibilities
Perform physical verification of full-chip and block-level layouts, including DRC, LVS, ERC, and other checks
Debug and resolve DRC / LVS violations by collaborating with design teams
Manage and maintain PV runsets and automate verification tasks using scripting
Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
10+ years of experience in ASIC or SoC physical verification or layout sign-off
Hands-on experience with sign-off tools such as Mentor Graphics Calibre and Synopsys ICV
Strong proficiency in Tcl, Python, or Shell scripting for automation
Familiarity with advanced CMOS technology nodes and PDK components
Verification Engineer • Oakland, California, United States