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Senior ASIC RTL Design Engineer for LPDDR6/DDR IP
Senior ASIC RTL Design Engineer for LPDDR6/DDR IPSynopsys, Inc. • Sunnyvale, CA, United States
Senior ASIC RTL Design Engineer for LPDDR6 / DDR IP

Senior ASIC RTL Design Engineer for LPDDR6 / DDR IP

Synopsys, Inc. • Sunnyvale, CA, United States
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A tech innovator in semiconductor solutions seeks a skilled digital design engineer in Sunnyvale, California. You will design ASIC blocks for advanced memory IP, write and verify RTL code, and debug simulation issues. The ideal candidate has 5 years of experience with a BSEE or 3 years with an MSEE, along with strong knowledge of RTL coding and familiarity with Synopsys EDA tools. Join a diverse team focused on innovation and technical excellence. Explore a range of generous benefits and rewards.

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