Design Verification Engineer

Required Skills & Experience

• 8–12 years of experience in SoC Verification
• Hands-on experience debugging complex SoC issues involving ARM subsystems.
• Verilog-HDL
• C test development at SoC level
• SV Assertions
• Protocol Knowledge (JTAG, SPI, UART, serial communication protocols and AMBA APB, AHB interconnect protocols)
• Gate-level simulation & SDF flows
• Hands on experience in Testbench Architecture & Development of new BFMs.
• Prior work on mixed-signal or digital-analog interface verification