Job Description
Job Details : Job Description :
Designs, implements, and verifies the layout design of test structures and circuits which enable the development of Intel's leading-edge silicon technologies. The test structures are tailored to model Quality and Reliability (QnR) parameters which are essential to the qualification life cycle for each technology.
You will have the opportunity to work with partners in Technology Development (TD), Design Technology Platform (DTP), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.
Primary responsibilities include but are not limited to :
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Additional responsibilities :
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Qualifications :
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and / or experience listed below would be obtained through a combination of your school, work and / or classes and / or research and / or relevant previous job and / or internship experiences.
Minimum Qualifications :
Layout design & Cadence Virtuoso
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Preferred qualifications :
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CMOS VLSI design concepts, flows, and EDA tools
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Job Type : Experienced Hire
Shift :
Shift 1 (United States of America)
Primary Location :
US, Oregon, Hillsboro
Additional Locations :
US, Arizona, Phoenix
Business group :
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly / test packages the compute devices to improve the lives of every person on Earth.
Posting Statement :
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N / A
Benefits :
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here :
Annual Salary Range for jobs which could be performed in the US : 121,050.00 USD - 227,620.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Layout Designer • Hillsboro, OR, US