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Senior Senior Virtual Test Engineer (Unable to consider OPT or CPT Candidates)
Senior Senior Virtual Test Engineer (Unable to consider OPT or CPT Candidates)Volkswagen of America • Belmont, California, US
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Senior Senior Virtual Test Engineer (Unable to consider OPT or CPT Candidates)

Senior Senior Virtual Test Engineer (Unable to consider OPT or CPT Candidates)

Volkswagen of America • Belmont, California, US
[job_card.30_days_ago]
[job_preview.job_type]
  • [job_card.full_time]
[job_card.job_description]

Role Summary

  • The Virtual Test Engineer will own the end‑to‑end test engineering for virtual ECUs—from V‑ECU creation (AUTOSAR Classic / Adaptive) and restbus / environment modeling, to deterministic simulation, fault injection, conformance, diagnostics / flash, and scalable CI execution. You will build and operate a virtual test platform that exercises production software stacks (communication, diagnostics, safety / security, OTA readiness) with measurable coverage and release‑grade. You partner with software, systems, safety, cybersecurity, HIL, and OTA teams to ensure the virtual pipeline finds defects earlier than HIL / vehicle, at fleet scale.
  • The position will be a member of the worldwide connectivity technical team and interfaces with multiple stakeholders of VW Group’s technical team members. This position investigates and develops new architectures for connected systems targeted to the US market.

Role Responsibilities

Operational Management - (35%)

  • Ownership of Virtual Test topics in NAR markets
  • Own the relationship with network operator, contract manufacturer, platform provider and lead strategic discussions and technical negotiations.
  • Serve as technical authority for V‑ECU testing; mentor engineers in XiL best practices, determinism, and modeling trade‑offs.
  • Drive supplier alignment (Tier‑1 / 2) for virtual deliverables (V‑ECU packages, ARXML / ODX / OTX, service catalogs, security plugins).
  • Conduct design / test reviews, DFMEA / FMEA, and lead 8D on defects discovered in SIL with crisp reproduction artifacts.
  • V ‑ ECU Build & Simulation Architecture – (35%)

  • Define the V‑ECU generation strategy for AUTOSAR Classic (RTE + BSW abstraction, virtual MCAL stubs) and Adaptive (POSIX targets, ara : : com SOME / IP bindings), including OS abstraction, timers, time‑warp, and determinism controls.
  • Select and integrate V‑ECU platforms (e.g., dSPACE VEOS / SystemDesk, Vector vVIRTUALtarget / CANoe4SW Server, ETAS COSYM / ASCET, AVL VIRTUAL TESTBED, Wind River Simics, Imperas / OVPsim, QEMU / Renode‑based flows) and manage tool qualification where applicable.
  • Establish co‑simulation topologies : MIL / Plant models (Simulink / Modelica / FMU / FMI), bus / network simulators, and virtualization of sensors / actuators with IO semantics and timing fidelity.
  • Communication, Diagnostics & Flashing in SIL – (10%)

  • Model and validate Automotive Ethernet stacks : SOME / IP & SOME / IP‑SD, DoIP, AVB / TSN where applicable; simulate VLAN / QoS and congestion scenarios.
  • Exercise CAN / CAN‑FD, LIN, FlexRay via restbus simulations; verify UDS services, ISO‑TP segmentation and XCP / CCP measurement / calibration flows.
  • Implement DoIP‑routed UDS flashing in SIL with eligibility / state checks, A / B or recovery slots, anti‑rollback, and bootloader handshake emulation (timings, NRCs).
  • Virtual Environment & Restbus Modeling – (10%)

  • Develop restbus models for gateways, sensors, actuators, and peer ECUs using Vector CANoe / CAPL (incl. CANoe4SW Server), Python, and co‑simulation bridges.
  • Build service catalogs and SOME / IP service mocks, including late‑joiner / re‑announce behaviors and instance collision tests; emulate SecOC / E2E protections.
  • Create plant models (Simulink / Modelica, FMU / FMI) for closed‑loop testing of control functions; parameterize with production DBC / ARXML / LDF.
  • Robustness, Fault Injection & Fuzzing – (5%)

  • Execute fault campaigns : bus saturation, frame loss / reordering, clock drift, time sync perturbations (gPTP), power cycles / brown‑outs (virt), memory pressure, and network fuzzing (UDS / DoIP / SOME‑IP).
  • Apply protocol fuzzing (boofuzz, Scapy, Peach, AFL++ harnesses), mutation testing, and error seeding to validate diagnostic / communication hardening.
  • Model electrical transients (ISO 7637‑2, load dump) effects at the software boundary and verify recovery logic within the V‑ECU.
  • CI ‑ at ‑ Scale & Test Data Ops – (5%)

  • Architect headless SIL farms (Docker / K8s runners, ephemeral test environments) executing parallel suites (thousands of SIL testcases per commit / nightly).
  • Integrate CI / CD (Jenkins / GitLab / Azure DevOps), artifact management (SBOM : SPDX / CycloneDX), test results (JUnit / Allure), and flaky test quarantine + triage dashboards.
  • Implement golden capture / compare pipelines (PCAP / MDF4 / CSV) and scenario versioning (OpenSCENARIO / OpenDRIVE / ASAM OSI if AD / ADAS is in scope).
  • Qualifications

    Skills Requirements :

  • Excellent strategically thinking and communication skills.
  • Analytical and conceptual thinking
  • Experience in developing strategies for R&D
  • Communication skills - interpersonal, presentation and written
  • Integration - joining people, processes or systems
  • Influencing and negotiation skills
  • Strategic / visionary minded
  • Resource management
  • Interest in designing systems
  • Specialized Skills

    Required

  • Knowledge of communication HW & SW architecture and hardware development processes.
  • Excellent communication; proven cross‑functional leadership across hardware, software, cloud, manufacturing, compliance, and program management.
  • Deep understanding of typical vehicle EE architectures and automotive development processes.
  • Deep expertise in SOME / IP / SOME‑IP‑SD, DoIP, UDS / ISO‑TP, CAN / CAN‑FD / LIN, and restbus modeling; hands‑on with ODX / OTX and XCP.
  • Proven delivery of CI‑scale virtual test grids (parallel headless execution, artifacted evidence, flake management).
  • Strong command of coverage engineering (MC / DC, model & code coverage), fault injection / fuzzing, and performance / timing analysis in virtual environments.
  • Demonstrated experience with MISRA, static analysis, sanitizers, and traceability (Polarion / Codebeamer).
  • Toolchain experience :

  • Networks & Middleware (experience with any of) :
  • Automotive Ethernet : SOME / IP & SOME‑IP‑SD, DoIP, TSN / AVB, VLAN / QoS
  • CAN / CAN‑FD, LIN, FlexRay, ISO‑TP
  • Diagnostics : UDS, ODX / OTX authoring / automation; XCP / CCP (ASAM), DIDs, routines, DTC handling
  • Security (where applicable) : SecOC (AUTOSAR), TLS / mTLS, E2E protection profiles
  • V‑ECU Platforms & Co‑Sim (experience with any of) :
  • V‑ECU generation : AUTOSAR Classic (RTE + virtual BSW / MCAL), Adaptive (POSIX, ara : : com), Android Automotive / QNX / Linux POSIX builds
  • Tools (any mix) : dSPACE, Vector vVIRTUALtarget / CANoe4SW Server, ETAS COSYM, AVL VIRTUAL TESTBED, Imperas / OVPsim, QEMU / Renode
  • FMU / FMI import, Simulink / Modelica co‑sim; ASAM XIL API test bench control
  • Restbus, Test Authoring & Automation (experience with any of) :
  • Vector : CANoe / CANalyzer / CANape, vTESTstudio, CAPL; CANoe4SW Server for headless SIL
  • Python (python‑can, scapy, pyshark, pyvisa), Robot Framework, pytest, gRPC / REST harnesses
  • Traffic / PCAP tooling : Wireshark (SOME‑IP / DoIP dissectors), tcpreplay, custom fuzzers
  • Coverage, Analysis & Observability (experience with any of) :
  • Desired

  • V‑ECU generation using VEOS / SystemDesk, vVIRTUALtarget / CANoe4SW, or COSYM; co‑sim with FMU / FMI and plant models.
  • TSN budget analysis (gPTP domains, Qav / Qbv scheduling) for AV / service traffic in SIL.
  • Virtual UDS flashing including A / B slots and anti‑rollback; security hardening (SecOC, TLS / mTLS) validated in SIL.
  • Experience scaling SIL in Kubernetes with observability (OpenTelemetry + ELK / Grafana) and SBOM / attestation in release flow.
  • Exposure to ADAS scenario‑based validation (OpenSCENARIO / OSI) and cloud‑scale simulation.
  • Knowledge of VW Group product design requirements,
  • Programming experience with the languages C, C++, Java, Python, and script languages.
  • Years of Required Experience

  • 7+ years of hardware or software development experience for connectivity functions in an vehicle manufacturer or supplier
  • 5+ years of working in automotive projects including communication technology, ADAS or automation
  • Education Requirements :

    Required

  • BS in Engineering
  • Desired

  • MS and / or PhD in Engineering
  • Work Flexibility :

  • Accommodation for working time zone differences between international locations as needed
  • Travel is estimated to be 10%.
  • Role requires flexibility in daily schedule, including early morning meetings with Europe, afternoons / evenings for the US West Coast or Asia
  • Travel is expected regularly to local development teams and partners
  • Salary is determined by geographical location and adjusted accordingly.  In Silicon Valley, the expected base salary range is between $160,000 - $175,000. Other benefits for this position include :

  • Eligibility for annual performance bonus
  • Healthcare benefits
  • 401(k), with company match
  • Defined contribution retirement program.
  • Tuition reimbursement
  • Company lease car program
  • Paid time off
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