A leading semiconductor company in San Jose is seeking a Senior Package Layout Engineer to join the System-in-Package team. This role involves designing complex SoCs for various industries, including IoT and Automotive, utilizing advanced 2.5D and 3D technologies. Candidates should have a degree in Electrical Engineering and at least 4 years of experience with Cadence APD & Allegro toolsets. The position offers a competitive salary and fosters a hybrid working environment.
#J-18808-Ljbffr
Senior Engineer • San Jose, CA, United States