Design Verification Engineer

Our client is a world-leading technology company at the forefront of semiconductor innovation, powering some of the most advanced digital systems in the industry. Their work touches billions of users globally, driving next‑generation performance and efficiency across highly complex hardware and software ecosystems.

They are seeking a Design Verification Engineer with deep expertise in SystemVerilog / UVM and digital ASIC verification. This role is critical for ensuring robust, reusable verification environments, achieving high functional coverage, and supporting rapid innovation in complex hardware designs that operate at massive scale.

What You’ll Do

• Develop comprehensive Core Verification Plans based on unit micro‑architecture and design specifications.
• Architect and implement reusable verification environments using SystemVerilog / UVM.
• Create and execute constrained‑random and directed tests to achieve high functional and code coverage for core units.
• Analyze simulation results, debug complex failures, and collaborate with design teams to root‑cause and resolve issues.
• Develop and maintain scripts (Python / Perl) to automate verification flows and regression management.
• Support verification of digital systems using standard IP components and interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Act as a technical leader within verification teams, providing feedback to RTL designers and IP architects.

Requirements

Nice‑to‑Have Qualifications (Not required, but beneficial)

Why This Role Matters

This position is central to delivering high‑performance, reliable digital hardware at global scale. You will have the opportunity to shape verification strategies, implement reusable test environments, and contribute to cutting‑edge projects that power complex systems used by millions worldwide. This is an environment where technical expertise meets massive real‑world impact.

#J-18808-Ljbffr