Design Verification Principal Engineer

Responsibilities

Duties in this position will include:

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Qualifications

· Bachelors Degree or above in EE/CS, minimum 7 years experience with HDL logic Design-Verification

· System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must

· Pre-existing Experience / familiarity with DDR DRAM technology a strong preference

· Working experience with Python and TCL scripting languages preferred

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.