A Silicon Valley hardware startup is seeking an experienced physical design engineer to define SOC assembly and optimize performance in AI infrastructure. Candidates should have at least 10 years of experience, a relevant master's degree, and proficiency in Innovus or Synopsys tools. Skills in Verilog and scripting are necessary. Join a world-class team and impact the next generation of AI solutions. The salary for this role ranges from $210k to $270k annually.
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Physical Design Engineer • San Francisco, CA, United States