Senior Wireless PHY Verification Engineer

A leading technology company in San Francisco seeks a PHY Design Verification Engineer to join its wireless silicon development team. The role involves pre-silicon RTL verification of wireless PHY and its interfaces, requiring advanced knowledge in Verilog and SystemVerilog, along with a minimum of 10 years of relevant experience. Offers competitive pay from $181,100 to $318,400, comprehensive benefits, and opportunities for employees to participate in stock programs.

#J-18808-Ljbffr