ASIC Design Principal Engineer

Job Description

Job Description

About Us :

nEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability.

Job Overview :

As an ASIC Design Principal Engineer at nEye, you will have primary responsibility for the development and design of the custom CMOS integrated circuit family that is part of the company’s SuperSwitch. This role will span the full ASIC development lifecycle, including architecture definition, design and verification, coordination with external CMOS design houses and fabrication foundries, and oversight of chip testing and validation. In addition to directing the test of the CMOS chip, you will be engaged with nEye Team Members in the strategic design, development, and implementation of all test procedures and systems to ensure the quality and performance of our SuperSwitch.

This role involves both technical execution and leadership responsibilities. You will work closely with nEye Si Photonics designers, System and Software Engineers, Packaging Engineers and MEMS / Process Engineers to design and implement testing protocols, troubleshoot issues, and contribute to the advancement of our photonics products.

Key Responsibilities

• Design and Engagement : (1) Design and develop custom CMOS ASICs (preferred analog focus), from initial architecture through tape-out. (2) Collaborate with external CMOS design houses for schematic capture, layout, and physical verification (DRC / LVS). (3) Engage with CMOS fabrication foundries to manage tape-out, mask generation, and production schedules.
• Testing & Quality :   (1)   Define and oversee test strategies for wafer- and package-level testing, including test fixture design and parametric test plans. (2) Analyze test results, identify performance issues, and implement design improvements or yield enhancements. (3) Ensure full documentation of design specifications, verification plans, and test reports. (4) Maintain project timelines, deliverables, and quality standards through close coordination with internal stakeholders and external vendors.
• Industry Standard : (1) Stay current with industry advancements and best practices in CMOS process nodes, EDA tools, and test methodologies.

Essential Skills & Qualifications

Preferred Skills

Benefits and Perks

Expected Salary Range and Title : $220,000-$280,000 annually.  Starting salary and title will depend on, and be commensurate with, relevant experience, skills, training, education, market demands, and the ultimate job duties and requirements.

nEye is an Equal Opportunity Employer . All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.