Silicon design package engineer

Hello there,

Happy Friday!

Hope you are doing well!'

We are hiring a position below on an urgent basis. If you are interested, please share your resume @ sadanandam.v@sstech.us or a pply here directly for immediate response.

Note

Only W2 candidates strictly and have a valid visa

Title : Silicon Design Package Engineer

Location : Santa Clara, CA (Hybrid)

Roles & Responsibilities :

This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies

Tools & Knowledge :

Mentor / Siemens and Cadence tools (especially for Package Layout Automation - PLA).

Technical Expertise :

Multi-layer package design experience.

Understanding of substrate manufacturing, Design Rules, and Assembly Rules.

Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.

Flip-chip package design concepts.

Thanks& Regards,

Sadanandam

sadanandam.v@sstech.us