Synopsys VCS Validation Engineer

Job Title : FPGA Verification Engineer

Location : Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri

Duration : 12+ Months

Mandatory Areas

Must Have Skills FPGA Verification Engineer

Skill 1 8 + Years of in FPGA

Skill 2 5 +Years of Exp in UVM

Skill 2 5 +Years of Exp in System Verlilog

Job Description :

Strong understanding of FPGA design principles and architectures.

Proficiency in System Verilog and UVM verification methodology.

Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).

Knowledge of code coverage and functional coverage analysis.

Excellent debugging and problem-solving skills.

Strong communication and collaboration skills.

Requirements :

Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

Experience in FPGA verification.

Experience with scripting languages (e.g., Python, Perl).

Familiarity with hardware description languages (e.g., VHDL, Verilog).

Rohit Chauhan