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IP Design Verification Engineer Intern - 2025
IP Design Verification Engineer Intern - 2025SK hynix memory solutions America Inc. • San Jose, CA, US
IP Design Verification Engineer Intern - 2025

IP Design Verification Engineer Intern - 2025

SK hynix memory solutions America Inc. • San Jose, CA, US
[job_card.variable_days_ago]
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  • [job_card.full_time]
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Job Description

Job Description

About the Company :

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Responsibility :

Study the Microarchitecture of the Design (IP) and list the Verification Requirements for testing.

  • Create the Test Bench for the IP testing.
  • Create all Tests Cases to fully test the functionalities of the IP.
  • Debug & identify the issue & file bug reports to Designer.
  • Testing to meet the Coverages (Functional, Conditional) criteria.

Minimum requirements :

  • Education in BSEE and MSEE.
  • Digital IC Design & Verification experiences.
  • Work in Windows and Linux environment.
  • C-Script or Perl equivalent experience.
  • Experience in System Verilog & UVM.
  • Experience in Perforce and Confluence.
  • COMPENSATION : $35 / hr - $45 / hr

    REGARDING COMPENSATION :

    The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

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