Principal Design Engineer

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

Specific responsibilities :

• Proficiency in logic design and micro-architecture
• Proficiency in Verilog / SystemVerilog and its simulation environment
• Good knowledge of IC design with high speed and low power
• At least six years experience working on digital IC development projects excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements :

The annual salary range for California is $136500 to $253500. You may also be eligible to receive incentive compensation : bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include : paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

Were doing work that matters. Help us solve what others cant.

Required Experience :

Staff IC

Key Skills

Design,Academics,AutoCAD 3D,Cafe,Fabrication,Java

Employment Type : Full-Time

Experience : years

Vacancy : 1

Monthly Salary Salary : 136500 - 253500