Low Power Design Engineer (contract)

Low Power Design Engineer

Duration : 12+ months

Hourly : W2 / 1099 / Corp-to-Corp

US Citizen or US Permanent Resident only

Locations : San Diego, Irvine or San Jose (onsite / no hybrid)

• You will work with Architects and Logic Designers to understand the power requirements and define power specifications / UPF.
• Support UPF for design / DV / implementation teams and verify and signoff low power intent using VCLP tool.
• Work closely with design, DV, implementation teams to define low power vectors, generate early and signoff power data using PTPX.
• Analyze power data and work closely with PD and design team to optimize for low power and improve overall PPA.
• Support in enhancing low power flows, work with tool vendors to address any power-related tool or flow issues.
• Hands-on skills in one of the scripting languages, Shell / TCL / Perl / Python.

PMIC {Power Management Integrated Circuits} GROUP on LinkedIn : https : / / www.linkedin.com / groups / 1903172 /