ASIC Design Engineer

A company is looking for an ASIC Design Engineer - Packet Processing & Ethernet.

Key Responsibilities :

Develop microarchitecture specifications for packet processor and high-speed pipelined data path designs

Implement RTL designs using Verilog / System Verilog for high-speed data paths and packet processing logic

Collaborate with verification engineers to create block- and system-level test plans

Minimum Qualifications :

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field

7+ years of post-college experience in digital design with proficiency in Verilog and System Verilog

Experience in RTL design for high-speed data paths or packet processing in ASICs

Deep understanding of Host Ethernet adaptor architectures

Familiarity with timing closure and modern physical design methodologies