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Physical Design Engineer
Physical Design EngineerInspire Semiconductor • Austin, Texas, United States, 78701
Physical Design Engineer

Physical Design Engineer

Inspire Semiconductor • Austin, Texas, United States, 78701
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  • [job_card.full_time]
[job_card.job_description]

About Us :

At InspireSemi, we're not just building chips; we're revolutionizing high-performance computing. Our groundbreaking architecture packs thousands of 64-bit CPU cores onto a single chip, all seamlessly connected. We're driven by a mission to make high performance computing more accessible, energy-efficient, and easier for developers to harness. Ready to make a real impact? Join our passionate team!

Why Join InspireSemi?

  • Be a Pioneer : Get in on the ground floor of a hypergrowth startup! You'll be part of a small, dynamic team shaping the future of computing.
  • Make an Impact : Your work will directly contribute to disruptive technology.
  • Grow With Us : Seize significant growth and development opportunities.
  • Rewarding Compensation : We offer a competitive salary, bonus potential, and meaningful equity.
  • Flexibility : Benefit from a hybrid work model (with potential for fully remote for exceptional candidates) and flexible time off.

The Opportunity : We’re looking for a talented and driven Physical Design Engineer to execute critical aspects of our chip implementation flow. In this hands-on role, you will be responsible for driving the physical design of cutting-edge SoCs from floorplanning through signoff. You’ll work closely with front-end design, verification, and other teams to deliver high-performance, power-efficient, and area-optimized silicon.

What You'll Do :

  • Own and drive block-level and top-level physical design through place and route (P&R).
  • Develop and optimize floorplans for complex IP blocks and SoC integration.
  • Implement and manage clock tree synthesis (CTS) and optimize clock distribution for performance and power.
  • Perform detailed routing and analyze timing, signal integrity, and power integrity issues.
  • Ensure physical design closure : Drive timing closure, power optimization, and DRC / LVS / ANT signoff.
  • Collaborate closely with front-end design teams to ensure seamless RTL to GDS handoff.
  • Contribute to and improve physical design flows, methodologies, and automation for better PPA and turnaround time.

    • What You Bring :

  • A Bachelor’s or Master’s degree in Electrical or Computer Engineering.
  • 5+ years of hands-on experience in physical design, including recent experience with advanced node Tape Outs (e.g., 3nm, 2nm).
  • Deep expertise in place and route using Cadence toolchain (Genus, Innovus, Tempus, Voltus).
  • Strong understanding of STA (Static Timing Analysis) and timing closure methodologies.
  • Solid understanding of clock tree synthesis, EM / IR drop analysis, DRC / LVS signoff, and ECO implementation.
  • Strong scripting skills (TCL, Python, Perl, BASH) for flow automation and efficiency improvements.
  • Excellent communication and teamwork skills – you thrive in a collaborative, fast-paced environment!

    • Bonus Points :

  • Knowledge of RISC-V-based SoCs or datacenter-class CPU designs.
  • Familiarity with hierarchical design methodologies.
  • Experience with low-power design and multi-voltage domain implementation.
  • Exposure to DFT insertion and ATPG flows.

    • If you're excited about pushing the boundaries of computing and working on truly innovative technology in a rewarding environment, we'd love to hear from you!

    PIb72cc514b542-30511-39166941

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    Design Engineer • Austin, Texas, United States, 78701

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