Software Architect FPGA

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THE ROLE :

We are seeking a highly experienced and motivated FPGA Software Architect to join our team in a key individual contributor role, with a strong potential to grow into a leadership position. This role focuses on the development and architecture of internal EDA tools with a deep emphasis on timing analysis, static timing analysis (STA), timing closure, and FPGA-specific clocking and configuration architectures.

THE PERSON :

The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD.

KEY RESPONSIBILITIES :

Design and architect software systems specifically targeting FPGA timing analysis and closure, including :

Development of internal EDA tools for static timing analysis (STA)

Clock tree modeling, propagation, and clock domain crossing analysis

Support for timing closure workflows across hardware / software interfaces

Collaborate closely with FPGA hardware architects and implementation teams to :

Integrate hardware timing models into software frameworks

Interpret hardware behavior for accurate software-level simulation and analysis

Own the technical roadmap for timing-centric EDA software tools within the FPGA design flow

Build scalable, modular, and high-performance software components for internal FPGA tools

Drive system-level architectural decisions considering performance, usability, and maintainability

Eventually lead and mentor a growing team of software and EDA engineers

Stay abreast of developments in FPGA architectures, timing methodologies, and EDA toolchains, bringing insights back into the product

Foster a culture of technical excellence, collaboration, and innovation

PREFERRED EXPERIENCE :

Experience in software development, w focused on FPGA or ASIC timing analysis and closure

Expert-level understanding of FPGA architectures, including :

Clocking structures and global / local routing

Configuration memory and programmable logic blocks

Timing constraints and analysis methodologies (e.g., SDC, STA)

In-depth experience with timing closure methodologies, including multi-corner, multi-mode (MCMM) analysis, false / exception path handling, and delay modeling

Strong proficiency in software architecture and systems programming :

Expertise in C++ / Python and scalable system design

Familiarity with parallel processing, memory optimization, and performance profiling

Prior experience with developing or extending internal EDA tools for FPGA or ASIC design flows

Proven ability to work effectively across disciplines (software, hardware, and architecture)

Comfortable in fast-paced, iterative development environments with high ownership

Demonstrated ability or potential to lead engineering teams, set technical direction, and mentor junior engineers

ACADEMIC CREDENTIALS :

• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.