Virtual Platform Hardware Modeling Engineer

Job Description

Job Description

We are seeking a modeling Engineer to develop high-level models of complex SoC hardware. The virtual platforms combine models of custom hardware accelerators for vision, 2D and 3D graphics, machine learning and more, within a multi-core, multi-level memory hierarchy SoC architecture, and serve as the primary simulation vehicle for system software and firmware. The ideal candidate will be proficient in hardware simulation using C++, and understand the firmware development processes.

Responsibilities

• Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…
• Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.
• Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP.
• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks.
• Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption.

Minimum qualifications

Preferred qualifications

California Pay Range

$70—$75 USD