Senior FPGA Design Engineer

Senior FPGA Engineer – Bay Area, CA

The role involves hands‑on RTL design using Vivado IP Integrator, debugging with laboratory equipment such as oscilloscopes and multimeters, and working with low‑speed communication protocols (I²C, UART, etc.). The engineer collaborates with cross‑functional teams to develop and implement robust FPGA solutions.

Responsibilities

Collaborate effectively with cross‑functional teams to deliver high‑quality solutions.

Develop and implement RTL and FPGA methodologies for robust designs.

Work confidently with lab equipment and ensure smooth debugging processes.

Apply practical knowledge of oscilloscope and multimeter for testing and validation.

Qualifications & Experience

Proficiency in RTL design and Vivado Flow (IP Integrator).

Solid debugging capabilities using lab tools.

Strong understanding of oscilloscope and multimeter for troubleshooting.

Awareness of protocols; familiarity with low‑speed protocols like I²C, UART, etc., is advantageous.

Ability to create scripts, maintain clear documentation, and streamline workflows.

Strong visualization skills for design and implementation.

Analytical mindset for problem‑solving and debugging complex issues.

Eligible Applicant Disclaimer

Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity / expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

#J-18808-Ljbffr