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ASIC Design Verification Engineer.
ASIC Design Verification Engineer.Kasmo Global • San Francisco, CA, United States
ASIC Design Verification Engineer.

ASIC Design Verification Engineer.

Kasmo Global • San Francisco, CA, United States
[job_card.variable_days_ago]
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  • [job_card.full_time]
[job_card.job_description]

Job Title : ASIC Design Verification Engineer.

Location : Bay Area (Onsite - Work from Office). - Ok with relocation. (no assistance) San Francisco Bay Area

Required Experience : 6+ Years.

Work Authorizations : Preferably GC and US citizens. h1b all visa need 1.5 years validity

work authorization, drivers license and references LinkedIn proper

  • need local

pv will send email to references and they have to reply over the email

Profile exp, in years 6-10 max ideally

About the Role :

We are seeking a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of experience in the field of verification. As an Individual Contributor, he / she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations.

Key Responsibilities :

  • Develop and implement test plans, test cases, and coverage metrics for ASIC verification.
  • Perform block-level and chip-level verification
  • Proficiency in SystemVerilog and UVM (Universal Verification Methodology) .
  • Exposure to CPU-based verification techniques is highly desirable.
  • Familiarity with Direct Programming Interfaces (DPI) is a plus.
  • Strong problem-solving and debugging skills, with a keen attention to detail.
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