Job Title: RTL Design Engineer
Location: Santa Clara, CA 95054 (100% REMOTE)
Duration: 12 Months Contract on W2.
Job Description:
Duties:
Responsible for RTL design using Verilog HDL for implementation and debug.
Read and comprehend Analog Macro level architectural specification.
Top Skills:
Modelling Analog-Mixed signal circuits in RTL, with experience in LDOs, BGs and EMC
Ability to run and debug LECC for design
Run quality check tool such as Spyglass Lint and fix issues.
Ability to provide direction on optimal/efficient hierarchical design of Analog-Mixed signal designs
Ability to run Co-Sim preferred
Ability to debug DV issues preferred
Experience:
7+ years' experience required
Education:
Bachelor's (required) or Master's in Computer Engineering
RTL Design Engineer • Santa Clara, California, United States
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