Design Verification EngineerAmadeus Search • San Francisco, CA, United States
Design Verification Engineer
Amadeus Search • San Francisco, CA, United States
[job_card.variable_days_ago]
[job_preview.job_type]
- [job_card.full_time]
[job_card.job_description]Strong experience (typically 5 + years) in design verification of digital IP in a hardware environment. Proficiency in SystemVerilog (or equivalent HDL), and verification methodologies (UVM / UVM‑like frameworks). Deep understanding of digital logic, microarchitecture (e.g., pipelines, memory subsystems, AXI / AMBA interconnects), timing, and clocking domains. Experience with functional coverage, constrained‑random verification, assertions, and testbench development. Familiar with simulation tools, emulation / prototyping flows, and regression automation. Excellent debug skills, ability to drive issues to resolution across cross‑functional teams. Bachelor’s or Master’s in Electrical Engineering / Computer Engineering or equivalent; advanced degree preferred. Strong communication and collaboration skills; ability to lead in a fast‑paced startup environment. Experience in AI / hardware accelerator domain (e.g., tensor cores, matrix engines, AI pipelines). Familiarity with low‑power design, clock gating, power domains, and verification of power / clock islands. Experience working with mixed‑signal or analog / mixed‑signal IP verification, or prototyping on FPGA / emulation platforms. Background in physical verification, synthesis flow, timing closure or floorplanning. Opportunity to design and verify cutting‑edge compute IP for AI workloads. Early‑stage startup with high autonomy, ownership and the ability to shape architecture and process. Competitive compensation, equity participation and benefits aligned with high‑growth startup norms. Collaborative, high‑velocity culture driven by innovation and ambitious goals.
Title
Design Verification Engineer – Internal IP
Location
Bay Area (hybrid) or Toronto
About the Company
A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‑edge AI workloads with custom silicon and software stacks.
Role Overview
You will lead verification efforts on internal IP blocks that power the company’s compute architecture. Working closely with design engineers and systems teams, you’ll define verification strategies, develop testbenches, write directed and random stimulus, debug failures, and sign off quality IP for integration into larger systems.
Key Responsibilities
- Review IP specifications and architecture to understand functional, performance, and integration requirements.
- Develop verification plans, create functional coverage models, define corner cases and failure modes.
- Build testbenches using SystemVerilog (or similar HDL), UVM or equivalent methodology, and integrate into simulation / acceleration / emulation flows.
- Automate regressions, monitor coverage metrics, identify gaps, and work with design teams to close them.
- Debug and triage simulation / emulation failures, analyze waveforms / traces, provide meaningful feedback to design and physical teams.
- Collaborate with RTL designers, synthesis and physical teams, CAD and systems / firmware teams to ensure smooth handoff and tape‑out readiness.
- Mentor or collaborate with other engineers to drive verification best practices and process improvements.
Qualifications
Nice to Have
What’s in It for You
#J-18808-Ljbffr
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