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Senior Design Verification Engineer (San Diego)
Senior Design Verification Engineer (San Diego)Globex Digital • San Diego, CA, US
Senior Design Verification Engineer (San Diego)

Senior Design Verification Engineer (San Diego)

Globex Digital • San Diego, CA, US
[job_card.variable_days_ago]
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  • [job_card.part_time]
[job_card.job_description]

Job Title : Verification Engineer (SystemVerilog / UVM)

đź“Ť Location : Sunnyvale, CA or Austin, TX

  • 514 years experience

Responsibilities

  • Develop and maintain UVM / SystemVerilog-based verification environments for IP, subsystem, and SoC-level testing.
  • Understand design specifications and create comprehensive test plans based on functional and architectural requirements.
  • Build directed and random test cases, perform coverage analysis, and ensure functional / code coverage closure.
  • Debug simulation failures and collaborate closely with RTL designers to resolve issues.
  • Execute regression runs, analyze results, and drive continuous improvements in verification processes.
  • Integrate and run power-aware simulations, perform low-power checks, and work with UPF / CPF as needed.
  • Collaborate with DFT, PD, RTL, and post-silicon validation teams to ensure design quality across domains.
  • Document test environments, test plans, and results for internal and external reviews.

    • Required Skills

  • Strong understanding of SystemVerilog (SV) and UVM , with excellent debugging skills.
  • Solid knowledge of AMBA protocols .
  • Experience in coverage-driven verification and regression management.
  • Familiarity with low-power verification methodologies and UPF / CPF flows.
  • Ability to work in cross-functional teams and deliver high-quality verification solutions.
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