Silicon Design Package Engineer - Santa Clara, CASaransh Inc • Santa Clara, CA, United States
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Silicon Design Package Engineer - Santa Clara, CA
Saransh Inc • Santa Clara, CA, United States
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Role : Silicon Design Package Engineer
Location : Santa Clara, CA
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies
Tools & Knowledge :
Mentor / Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise :
Multi-layer package design experience.
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Flip-chip package design concepts
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Silicon Design Engineer • Santa Clara, CA, United States
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