Document controller Jobs in Roseville, CA

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE TEAM

The AECG x86 Embedded Team builds and optimizes x86 platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.

THE ROLE:

As a member of the AECG-Embedded X86 SOC architecture team, you will help bring to life cutting-edge designs. You will work closely with IP design, Physical Design teams, and product engineers to achieve first pass silicon success.THE PERSON:

A successful candidate will work with senior silicon architects. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.KEY RESPONSIBLITIES:

• Lead SoC architecture: define processor complex, interconnect/NoC, memory controllers/DRAM topology, IOMMU hierarchy, security islands, and subsystem boundaries; write clear architecture specifications and drive reviews to closure.
• Own platform power & reset intent: specify PWROK/PWROKRAW/reset/iso sequencing across rails and domains; ensure asynchronous PWROK de‑assertion behavior meets EGADS and safety requirements; partner with board/VR teams and FCH/ART owners.
• SOC Features ownership: Define and drive SOC features
• Static timing analysis definitions: work with IP, process and product teams to define STA strategies
• High‑speed I/O architecture: architect PCIe Gen5/Gen6 RC/EP topologies, NTB links, Ethernet MAC/PHY integration, clocking, lane bifurcation, and PHY interfaces; align controller programming models with NBIO/SYSHUB wrappers.
• Performance, power, and reliability modeling: establish CAC targets for GFX/NPU, guard‑bands/aging models using ARO/RO monitors, and close V/F/tj operating points with mission profiles; collaborate with quality teams on long‑life reliability.
• Functional safety (FuSa) & RAS: work with IP teams to allocate FuSa and RAS requirements, trace to Jama/PRS, and align external auditors and customer expectations; ensure ISO‑26262 compliance plans are executable.
• Cross‑functional leadership: partner with program management and customer engineers on headline specs (CPU/GPU/NoC sizing, DRAM speed/width, PCIe/Ethernet/NTB), schedules, and deliverables; clarify AMD vs. customer roles and responsibilities.
• Documentation & reviews: maintain MAS/mPRS/PRS artifacts, reset/power specs, and architectural confluence pages; drive HLD concept exits and LS[ABCD] milestones.

PREFERRED EXPERIENCE:

• X86, GPU, interconnect, HSIO, Memory subsystems architecture
• RAS
• Performance and Power bounding box definitions
• Familiarity with BIOS/FW/SW/Systems
• Embedded markets (automotive/networking/industrial)
• SOC design and execution

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-RW1

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE TEAM

The AECG x86 Embedded Team builds and optimizes x86 platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.

THE ROLE:

As a member of the AECG-Embedded X86 SOC architecture team, you will help bring to life cutting-edge designs. You will work closely with IP design, Physical Design teams, and product engineers to achieve first pass silicon success.THE PERSON:

A successful candidate will work with senior silicon architects. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.KEY RESPONSIBLITIES:

• Lead SoC architecture: define processor complex, interconnect/NoC, memory controllers/DRAM topology, IOMMU hierarchy, security islands, and subsystem boundaries; write clear architecture specifications and drive reviews to closure.
• Own platform power & reset intent: specify PWROK/PWROKRAW/reset/iso sequencing across rails and domains; ensure asynchronous PWROK de‑assertion behavior meets EGADS and safety requirements; partner with board/VR teams and FCH/ART owners.
• SOC Features ownership: Define and drive SOC features
• Static timing analysis definitions: work with IP, process and product teams to define STA strategies
• High‑speed I/O architecture: architect PCIe Gen5/Gen6 RC/EP topologies, NTB links, Ethernet MAC/PHY integration, clocking, lane bifurcation, and PHY interfaces; align controller programming models with NBIO/SYSHUB wrappers.
• Performance, power, and reliability modeling: establish CAC targets for GFX/NPU, guard‑bands/aging models using ARO/RO monitors, and close V/F/tj operating points with mission profiles; collaborate with quality teams on long‑life reliability.
• Functional safety (FuSa) & RAS: work with IP teams to allocate FuSa and RAS requirements, trace to Jama/PRS, and align external auditors and customer expectations; ensure ISO‑26262 compliance plans are executable.
• Cross‑functional leadership: partner with program management and customer engineers on headline specs (CPU/GPU/NoC sizing, DRAM speed/width, PCIe/Ethernet/NTB), schedules, and deliverables; clarify AMD vs. customer roles and responsibilities.
• Documentation & reviews: maintain MAS/mPRS/PRS artifacts, reset/power specs, and architectural confluence pages; drive HLD concept exits and LS[ABCD] milestones.

PREFERRED EXPERIENCE:

• X86, GPU, interconnect, HSIO, Memory subsystems architecture
• RAS
• Performance and Power bounding box definitions
• Familiarity with BIOS/FW/SW/Systems
• Embedded markets (automotive/networking/industrial)
• SOC design and execution

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-RW1

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.