Location: Santa Clara-Bay Area, CA (Onsite- 5 days a week)
Hire Type: Fulltime and contract (long term)
JOB DESCRIPTION:
System Verilog, UVM Good knowledge in AMBA,AX4,AHB IP/SS/SOC verification experience Test Env, test case development Regression debug, coverage analysis Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3 Experience in Synopsys/Cadance Tools usage
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RTL Verification Engineer • Santa Clara, CA, United States