Python programming Jobs in Hillsboro, OR

Sr Manager Validation / Verification Eng

The Hiring Manager is open to hiring at a Manager / Sr. Manager level for this position.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years in the lab, hands on oscilloscopes and network analyzers, watching silicon behave in ways the simulation never predicted. You know that the gap between a design that works on paper and one that ships is filled with late nights debugging signal integrity issues, hunting down noise sources, and figuring out why the eye diagram looks nothing like it should. You have done the work yourself, and now you know how to lead others through it.

Managing people energizes you, especially when those people are a mix of analog designers who think in differential pairs and hardware engineers who think in board stackups. You translate between these worlds naturally because you have lived in both. You know when to step into a debug session and when to let your team figure it out. You see patterns across test failures that others miss, and you can explain what is happening in a way that gets everyone pointed in the same direction.

At Synopsys, you will lead validation for high-speed SerDes PHYs that go into real products. The lab is well-equipped, the problems are hard, and your team will look to you to make the call when things get messy.

What You'll Be Doing

• Lead a cross-functional Silicon Validation team of analog designers and hardware engineers testing high-speed SerDes PHY implementations in a state-of-the-art lab
• Own the review and debug process for silicon under test, guiding your team through signal integrity issues, performance anomalies, and circuit behavior investigations
• Oversee characterization test execution and the creation of detailed test reports that meet project timelines and quality standards
• Coordinate the development of custom test boards and hardware solutions to support debugging, characterization, and bring-up activities
• Mentor team members on debugging techniques, lab equipment usage, and the application of analog circuit theory to explain real-world silicon behavior
• Collaborate with design, product engineering, and IP teams to align validation results with project goals and drive design improvements
• Build and maintain a lab environment that supports effective testing of high-speed interfaces including USB, PCI Express, SATA, and Ethernet

What You'll Need

• Bachelor's degree in Electrical Engineering or related field, advanced degree preferred
• Extensive hands-on experience in analog IC circuit design and validation, specifically with high-speed circuits and SerDes PHYs
• Proven track record leading and managing technical teams, ideally cross-functional groups with both design and hardware engineering backgrounds
• Strong debugging skills using lab equipment including oscilloscopes, network analyzers, and high-speed probing tools
• Solid understanding of high-speed interface protocols such as USB, PCI Express, SATA, and Ethernet
• Experience with NRZ and PAM4 encoding techniques and their impact on signal integrity and testing
• Familiarity with software programming in MATLAB or Python for test automation and data analysis is a plus, basic knowledge of FPGA programming in Verilog is advantageous

The Impact You Will Have

• Enable successful tape-outs by catching and resolving silicon issues early, and accelerating time to market for high-speed SerDes IP
• Build a validation team that becomes known internally for thorough characterization, clear test reports, and reliable data that design teams trust
• Improve debug efficiency across the team by establishing best practices, mentoring on advanced techniques, and creating reusable test frameworks
• Contribute directly to the quality and competitiveness of Synopsys SerDes IP by ensuring silicon meets performance specifications under real-world conditions
• Strengthen collaboration between analog design and hardware engineering, creating a validation process that catches issues neither group would find alone
• Develop engineers who can move fluidly between theory and practice, building bench skills and circuit intuition that make them stronger contributors
• Shape lab infrastructure and tooling decisions that will support SerDes validation for the next generation of high-speed standards

Who You Are

• You can walk into a debug session where the team is stuck, look at the scope trace, ask three questions, and point them toward the actual problem
• You balance giving your team autonomy with staying close enough to catch when they are heading down a path that will not work, and you course-correct without making them feel micromanaged
• You explain circuit behavior and test results clearly to both technical and non-technical stakeholders, turning a messy set of waveforms into a two-sentence summary that a program manager can actually use
• You stay current on high-speed design trends and testing techniques because you know that what worked for 28 Gbps SerDes does not always translate to 112 Gbps PAM4
• You build team culture around rigor and curiosity, where people feel comfortable saying "I do not know why this is failing yet" and then methodically figuring it out together
• You manage competing priorities across multiple projects without losing sight of what actually matters, which test needs to finish this week and which one can wait

You will lead the Silicon Validation Engineering team in Hillsboro, a cross-functional R&D group focused on developing and validating high-speed SerDes PHYs. Your team includes analog designers and hardware engineers working together in a state-of-the-art test lab equipped with high-speed testing equipment. This team is responsible for ensuring that SerDes IP meets performance specifications and is ready for customer integration.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.