Technical program manager h1.location_city

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

In this role as Senior Technical Program Manager, you will be part of and working directly with the High-Speed IO/SerDes mixed signal IP (MSIP) design engineering teams coordinating the IP design deliveries to the various AMD SOC products on committed schedule and per standard quality metrics.

THE PERSON:

The Technical Project Manager will be involved in cross-functional MSIP projects from inception to post-silicon validation completion and participate in enabling the MSIP life cycle – planning, organizing, executing, and monitoring it, while ensuring these projects are on time, on quality, on budget, and within scope

KEY RESPONSIBILITIES:

• Work internally with the MSIP cross functional teams on planning for next-generation IPs (features, scoping, PPA targets, milestones, QA metrics, etc.)
  Participate in driving MSIP development cycle all the way thru silicon validation, bug tracking, design IP readiness reviews, and signoffs
• Track design convergence activities and focus the design teams on meeting near-term milestones and unblocking technical issues by pulling together the relevant functional/technical specialists and domain experts.
• Pull together next level periodic program-level management communication driving critical issues escalation where/as needed
• Collaborating with engineering CAD and release teams to manage deliverables and dependencies for analog/mixed signal IP developments.
• Participate in internal and SOC lessons learned and process improvements based on previous experiences.
• Work with IP and engineering leadership to set timelines, establish goals and quality metrics, manage expectations, and troubleshoot issues as needed, ensuring valuable and timely deliverables
• Work with IP leads interacting with internal and external stakeholders from various technical and functional backgrounds, and to maintain excellent working relations at all levels.
• Work with IP lead to manage and control communication plans and to drive project execution, track delivery, expect, monitor, and control change, own change management, proactively seek and resolve blockers
• Liaison / coordinate with various SOC PM teams to ensure adherence to project plans /schedules. Work with functional departments to clearly define and communicate engineering processes
• Contribute to building and maintaining project dashboards across multiple sites.
• Manage dashboards with intent of helping IP management and lead and other key stakeholders quickly review performance, identify issues, and track recovery actions. Communicate weekly MSIP progress and dashboard summaries consolidated from multiple internal/external sources as required.

PREFERRED EXPERIENCE:

• Strong semiconductor design technical background (e.g. mixed signal IP and/or hardware development) with solid fundamentals and good knowledge of semiconductor design fundamentals and lifecycle.
• Experience working with analog/mixed IP design teams or design management highly desirable.
• Background or knowledge in SOC workflows and physical design is desired.
• Excellent communication, executive presentation, organizational skills that has the ability to network well and stay connected into all the various groups and technologies. Strong time and task management skills with constant attention to details.
• Self-motivated and proactive with demonstrated creative and critical thinking capabilities with the ability to drive a team forward Understands and deals well with MSIP development cycles; remains flexible and calm in the face of uncertainty Teamwork - the candidate must be able to fit in well with a team, understand capabilities and priorities while fostering a collaborative environment.
• Able to scale collaboration across multiple geo sites and multiple design functions throughout the entire AMD organization.
• Able to build trust and lead through influence. Comfortable navigating tough situations, balancing priorities, and handling constraints while running sophisticated, fast-paced MSIP development projects. Problem solver - when an issue arises, the candidate must be able to navigate cross functionally to get it resolved. Driven to continuously improve team processes, methodologies, and tools.

ACADEMIC CREDENTIALS:

• Bachelors or Masters with relevant experience in technical program management

LOCATION: San Jose, CA

This role is not eligible for visa sponsorship

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.