Verification engineer Jobs in Mesa, AZ

Basic Qualifications

Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.

Clearance Requirements:

Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, citizenship is required.

Responsibilities for this Position

Primary Job Qualifications:

We encourage you to apply if you have any of these preferred skills or experiences:

• In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
• In-depth knowledge ofSystem Verilogobject orientedprogramming and theUniversal Verification Methodology (UVM)UnderstandsUVM TestbenchArchitectures Comfortable using and developing UVMagents, bus functionalmodelsUnderstands different types ofcoverage, usage of cover classes, cover points, etcExperience with predictive testbench components,functional coverageandassertionsExperience withconstrained randomtestingExperience with theRegister Abstraction Layer
• Familiarity withrequirements-based verification, requirement tracing, and developing requirement verification strategies etc
• Experience with scripting languages such as Linusshell scripts, TCL, Python
• Familiarity with usingFormalVerification tools, code coverage, writing waivers etc
• Familiarity with the following are also helpfulQuesta Verification IP (QVIP)Developing UVM testbenches for designs implemented inXilinxdevices with XilinxIPandSoCs AXIprotocols, PCIe, Space Wire, and Ethernet interfaces DSPfunctions and common signal processing componentsFamiliar with debugging FPGA/ASIC hardware and assisting with HW/SW integrationContinuous Integration features ofGITLab

Duties and Tasks:
• Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
• Determines architecture, system simulation and detailed design approach
• Defines module interfaces and all aspects of device design and simulation
• Creates test and simulation plans that establish functional criteria
• Verifies test results and analyzes performance
• May also review vendor capabilities and simulation tools
• Participates in the improvement of the ASIC/FPGA organizational processes
• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
• May provide leadership and/or direction to lower level employees
• Independently determines approach to solutions
• Contributes to the completion of major programs and projects
• Plans and executes project tasks for activities described above

General Knowledge, Skills and Abilities:
•This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.
• Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
• Proficient in the principles and techniques of ASIC/FPGA design and the design process
• Keeps abreast of technology trends
• Proficient awareness of business objectives and Engineering’s role in achieving
• Proficient in Microsoft Office applications
• Proficient written and verbal communications skills
•Ability to think creatively
• Ability to multi-task
• Proficient skill in communicating issues, impacts, and corrective actions
• Regular contact with senior levels of internal work groups
• Works under limited direction
• Contact with project leaders and other professionals within the Engineering department and with project teams across the company
• Some contact with external customers

Workplace Options:
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of the Scottsdale, AZ team. Learn more at

Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing

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Target salary range: USD $148, - USD $165,;This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.