Verification engineer • usa
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio.Coherency Verification Enginee.If you're looking for an exciting opportunity to grow in a innovative en... Show more
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Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence).Strong proficiency in System Verilog Assertions (SVA) and formal property specification.Experience with formal verificatio... Show more
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If you are a first time user, please create your candidate login account before you apply for a job.If you already have a Candidate Account, please Sign-In before you apply.Broadcom’s ASIC Product ... Show more
Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence).Strong proficiency in System Verilog Assertions (SVA) and formal property specification.Experience with formal verificatio... Show more
At AMD, we believe technology can change lives for the better.It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us.And we're looking for ta... Show more
Lead block-level functional verification for complex CPU/GPU SoCs using directed and constrained-random simulation.C/C++ in Linux, OOP/STL, and Verilog/SystemVerilog (Formal Verification / 7+ years... Show more
Job Title: RTL Verification Engineer </b><br /> <b>Location: Santa Clara, CA --Bay Area, CA is also ok.Duration : Long Term Contract </b></p> <p><br /> &... Show more
The average salary range is between $ 114,126 and $ 191,048 year , with the average salary hovering around $ 145,794 year .
At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Coherency Verification Engineer to join one of our clients' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.
Responsibilities:
Verify complex digital designs at RTL level according to architecture and design specifications.
Develop and maintain verification environments using SystemVerilog and UVM.
Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.
Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.
Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.
Run and manage simulations, regressions, and debug failures using industry-standard verification tools.
Apply both formal and dynamic verification methodologies to identify design issues early.
Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.
Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.
Track, document, and communicate verification progress, bugs, coverage status, and technical risks.
Contribute to continuous improvement of verification methodology, tools, and best practices.
Master or PhD
English C1
Industrial experience +8 years
Proficiency in SystemVerilog and UVM
Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
Experience with simulation and simulation tools
Knowledge of revision control methodology and tools (git, svn)
Experience in block level and sub-system or top level verification
Experience with formal and dynamic verification
Strong problem-solving skills and attention to detail
Excellent communication and teamwork abilities
Knowledge of the CHI protocol
Understanding of caches' structure and parameters
Experience in verification of coherent systems
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