Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.

THE ROLE:

We are seeking a motivated and detail-oriented Verification Engineer to join our DDR PHY IP development team. As an entry-level engineer, you will play a key role in verifying high-performance DDR PHY intellectual property used in cutting-edge SoCs across data center, mobile, and automotive markets. You’ll work closely with experienced design and architecture teams to develop robust verification environments, ensure design correctness, and contribute to silicon success

THE PERSON:

The ideal candidate is a passionate and driven engineer with a strong foundation in digital design. You are detail-oriented, eager to learn, and excited by the challenge of working on complex DDR PHY IP used in high-performance systems. You thrive in collaborative environments, take initiative in solving technical problems, and communicate clearly with both design and verification teams. Above all, you are motivated to grow your expertise in memory interface technologies and contribute to delivering reliable, high-quality silicon products.

KEY RESPONSIBILITIES:

• Develop and maintain UVM-based verification environments for DDR PHY IP.
• Write and execute test plans, directed and constrained-random tests, and functional coverage models.
• Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
• Create and maintain verification collateral, including testbenches, checkers, and scoreboards.
• Perform regression runs, track functional coverage, and ensure full design verification closure.
• Contribute to automation scripts for regression, data analysis, and verification efficiency improvements.

PREFERRED EXPERIENCE:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design fundamentals (clocking, timing, state machines, analog design basics).
• Experience with SystemVerilog and UVM (academic or internship exposure preferred).
• Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Basic understanding of DDR memory protocols and PHY architecture is a plus.
• Proficiency in scripting languages (Python, Perl, or TCL) for automation.
• Excellent analytical, debugging, and communication skills.
• Enthusiasm for learning and problem-solving in a collaborative, fast-paced environment.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred

LOCATION: Santa Clara, CA

This role is not eligible for visa sponsorship.

#LI-SL3

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

We are seeking a motivated and detail-oriented Verification Engineer to join our DDR PHY IP development team. As an entry-level engineer, you will play a key role in verifying high-performance DDR PHY intellectual property used in cutting-edge SoCs across data center, mobile, and automotive markets. You’ll work closely with experienced design and architecture teams to develop robust verification environments, ensure design correctness, and contribute to silicon success

THE PERSON:

The ideal candidate is a passionate and driven engineer with a strong foundation in digital design. You are detail-oriented, eager to learn, and excited by the challenge of working on complex DDR PHY IP used in high-performance systems. You thrive in collaborative environments, take initiative in solving technical problems, and communicate clearly with both design and verification teams. Above all, you are motivated to grow your expertise in memory interface technologies and contribute to delivering reliable, high-quality silicon products.

KEY RESPONSIBILITIES:

• Develop and maintain UVM-based verification environments for DDR PHY IP.
• Write and execute test plans, directed and constrained-random tests, and functional coverage models.
• Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues.
• Create and maintain verification collateral, including testbenches, checkers, and scoreboards.
• Perform regression runs, track functional coverage, and ensure full design verification closure.
• Contribute to automation scripts for regression, data analysis, and verification efficiency improvements.

PREFERRED EXPERIENCE:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design fundamentals (clocking, timing, state machines, analog design basics).
• Experience with SystemVerilog and UVM (academic or internship exposure preferred).
• Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Basic understanding of DDR memory protocols and PHY architecture is a plus.
• Proficiency in scripting languages (Python, Perl, or TCL) for automation.
• Excellent analytical, debugging, and communication skills.
• Enthusiasm for learning and problem-solving in a collaborative, fast-paced environment.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred

LOCATION: Santa Clara, CA

This role is not eligible for visa sponsorship.

#LI-SL3

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.