Principal Engineer, Digital IC Design and Architecture

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Join our Automotive OpenGMSL Team as a Principal Engineer - Digital IC Design and Architecture!

Help shape the future of intelligent, connected vehicles. We are looking for an experienced and innovative engineer to lead the architecture and design of next-generation connectivity solutions that power advanced automotive systems.

Our technology is at the heart of modern vehicle electronics, enabling the reliable transport of multi-Gigabit high-speed video, sensor, and control data across increasingly sophisticated vehicle networks. Trusted by leading automakers around the world and deployed in millions of vehicles, our solutions support applications ranging from digital cockpits and camera systems to advanced driver assistance and autonomous driving technologies.

Beyond automotive, OpenGMSL technology is also enabling innovation in industrial automation, medical imaging, and robotics. As part of our team, you will help develop the technologies that connect the next generation of machines and vehicles.

The position is based in Beaverton, Oregon, or Colorado Springs, Colorado.

Responsibilities:

· Digital Architecture and Design: Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including Gigabit‑speed serial interfaces and video and data routing solutions.

· Develop Next‑Generation Technologies: Drive the evolution of OpenGMSL technology through the development of new architectures, authoring and advancing of OpenGMSL technical standards, and active participation in industry standards organizations and committees.

· Specification Ownership: Write detailed block and subsystem-level specifications for design and implementation.

· RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems, and top‑level designs.

· Verification and Coverage Closure: Develop block‑level testbenches, verify block functionality, and collaborate with verification teams to achieve full‑chip verification and coverage closure.

· Digital Backend: Perform block‑ and top‑level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure.

· Mixed‑Signal Integration: Communicate closely with mixed-signal designers and verification engineers to support mixed‑signal simulations and real‑number modeling across the analog/digital boundary.

· Documentation and Design Reviews: Prepare technical documentation and lead architecture, design, and peer reviews.

· Lab Evaluation and Debug: Support silicon bring‑up, characterization, and debug activities.

· Cross‑Functional Collaboration: Collaborate across analog, digital, verification, test, and product definition teams to define requirements, support production test development, and ensure successful product execution.

· Technical Leadership: Provide technical leadership for complex SerDes subsystems and products.

Minimum Qualifications:

· MSEE or Equivalent: Master's degree in Electrical Engineering or equivalent with 7+ years of relevant experience or PhD with 4+ years of relevant experience.

· Digital Design: Experience designing and verifying complex digital systems using Verilog/SystemVerilog.

· System Architecture & Implementation: Demonstrated ability to architect and plan designs at the system level, translating high-level product concepts into robust design implementations.

· Communication Skills: Clear and concise written and verbal communication skills, with team working experience and a proactive approach to problem-solving.

· SerDes & Communications Expertise: Understanding of communication theory, high-speed SerDes transceiver architectures, and video/data transport.

· Design Trade-Offs & Physical Implementation: Solid understanding of digital and analog design trade-offs, with experience in timing analysis, power estimation, physical design, and DFT concepts.

· Lab & Silicon Debug Experience: Hands-on experience with silicon bring-up and debug

· Proven Track Record: Demonstrated success designing, leading, and introducing products to the market.

Preferred Qualifications:

· SerDes Standards and Protocols: Expertise in high-speed SerDes standards and protocols, including Ethernet, USB, PCIe, and/or video (DisplayPort, CSI/DSI, HDMI)

· Technical Standards Experience: Experience authoring SerDes technical standards and/or participating in industry standards committees.

· Behavioral Modeling: Experience with behavioral modeling, including verification of mixed-signal systems with behavioral modeling.

· DSP Design: Proficiency in Matlab and design of DSP blocks, including digital filters and signal-processing algorithms.

· Team Leadership: Experience leading teams and/or projects.

Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $157,080 to $227,460.

• Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

• This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.

• This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.