DFT MBIST Staff Engineer

Role: DFT MBIST Staff Engineer
Location Remote (must be aligned with PST time zone)

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About The AES Group
The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that have the greatest positive impact on society. AES has helped over 40 business enterprises, including Fortune 500 companies, engage their customers, empower their employees, and transform their business operations with the power of cloud, data, AI, engineering, and other emerging technologies.

Position Overview
We are seeking an experienced DFT MBIST Staff Engineer to join our SoC Design-for-Test (DFT) team. This is a hands-on role focused on Memory BIST (MBIST) implementation using Synopsys MBIST/SMS.
The ideal candidate will have strong experience owning the complete MBIST lifecycle, including insertion, integration, verification, simulation, pattern generation, diagnostics, and silicon bring-up, while working independently with minimal supervision. Key Responsibilities

• Perform MBIST insertion for complex SoC designs using Synopsys SMS.
• Integrate and verify MBIST at the top-level SoC.
• Develop, execute, and debug MBIST simulations using Synopsys VCS.
• Perform RTL, no-delay gate-level, and with-delay/timing-aware simulations.
• Generate and validate MBIST test patterns using VecGen.
• Debug RTL, simulation, MBIST integration, and memory-related issues.
• Support silicon bring-up, characterization, and post-silicon debug.
• Troubleshoot memory failures and DFT infrastructure issues.
• Work closely with DFT, RTL, Physical Design, and Product Engineering teams.
• Perform root-cause analysis and independently drive issues to resolution.
• Document MBIST implementation flows, debug procedures, and findings.

Required Qualifications

• 8+ years of hands-on DFT experience, with significant MBIST expertise.
• Strong hands-on experience with Synopsys MBIST (SMS5/SMS6).
• Proficiency with Synopsys VCS for MBIST simulation and verification.
• Strong understanding of the complete MBIST flow, including:
  • MBIST insertion and integration
  • Top-level verification
  • Pattern generation using VecGen
  • Diagnostics and debug
  • RTL and gate-level simulation
• Strong knowledge of MBIST algorithms, including March algorithms.
• Experience with memory repair schemes such as BIRA/BISR, redundancy analysis, and spare row/column allocation.
• Experience with no-delay and with-delay simulations.
• Hands-on experience with silicon bring-up and post-silicon debug.
• Strong RTL, MBIST, and simulation debugging/root-cause analysis skills.
• Experience working with complex SoCs containing multiple memory instances.
• Proficiency with Verilog/SystemVerilog and standard DFT methodologies.
• Ability to work independently with minimal supervision.

Preferred Qualifications

• Experience with advanced SoC DFT integration.
• Familiarity with ATPG and scan insertion flows.
• Scripting experience with Tcl, Perl, or Python.
• Experience working in fast-paced semiconductor product development environments.