Verification Engineer
stellent it • San Jose, CA, United States
4 hours ago
Job type
- Full-time
- Quick Apply
Job description
Hello,
Title :: Verification Engineer
Location :: San Jose, CA
Job Type- Fulltime
Below is the job description ::
- Test bench development using System Verilog UVM.
- Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections.
Requirements:
- 10+ Design Verification experience.
- Deep knowledge about System Verilog, UVM and verification coverage matrix.
- Strong experience with PCIe.
- Very familiar with the peripheral protocols such as UART, I2C, SPI Flash.
- Proficient in Python or Perl scripting.
- Programming experience with C/C++.
Best Regards,
Ishika
SR. IT Technical/Engineer Recruiter
Ph No- 321-421-1732
Email: ishika.azad@stellentit.com
Address: 505 Knolle Court, Saint Augustine, FL 32092