Structural engineer Jobs in Santa Clara, CA

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Job Description:

Broadcom Core Switching Group(CSG) is seeking a Logic Design Engineer focused on Packet Processing for our high performance Ethernet switch chip. In this position, you would be joining an innovative team that designs and builds the hardware, software and networking technologies that power the infrastructure of the leading data centers in the world.
The Core Switch Group (CSG) at Broadcom focused on developing high-performance Ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks. Our group is recognized as an industry leader in merchant silicon, enabling massive network bandwidth for AI infrastructure and cloud applications

Our organization works on all levels of ASIC development, spanning high-level architecture, to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a Logic Design Engineer.
As a Logic Design Engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant RTL for implementing components of complex networking ASICs.
This role requires participation through the full program lifecycle: developing micro-architecture specifications, RTL implementation, unit verification, timing convergence, ECO implementation, debug analysis and reviews.

Qualifications
The ideal candidate should exhibit the following behavioral traits:
. Thoughtful and perceptive analytical ability.
. A genuine curiosity for understanding the complete system.
. Dedicated to creative problem solving.
. Ability to work independently and at various levels of abstraction.
. Committed to getting things done and executing to plan

Minimum Qualifications:
. B.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
. B.S. with 8 years of experience, or M.S. with 6 years of experience in digital design on multiple networking ASICs.
. 4+ years of experience in Verilog based RTL design or verification, in deep submicron technologies.
. Familiarity with Ethernet and other networking protocols.

Preferred Qualifications:
. Extensive experience with Ethernet, TCP/IP, MPLS, tunneling and other networking protocols.
. Extensive experience with packet processing architectures packet parsing, ACLs, metering, policing, etc.
. Experience achieving timing closure on high performance ASICs, in deep submicron technologies.
. Experience with low power design techniques, power estimation methods, clock domain crossing techniques.
. Experience with scripting languages, such as Python or Perl.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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